1. Field of the Invention
The invention pertains to hermetic electrical device packaging generally and specifically to packages of high density commonly encountered in multichip modules. The invention provides protected test sites as an integral part of the package to allow for greatly enhanced package densities.
2. Description of the Related Art
The prior art is best illustrated by Olenick et al in U.S. Pat. No. 5,041,695, incorporated herein by reference. Therein they illustrate a multilayer hermetic package for electronic components having a multilayer substrate. A top surface of the multilayer substrate is used to mount electronic devices. A sealing cover seals to the top of the substrate and seals the components therein. Conductive pads at the outer edges of the substrate are provided outside the sealed area. Conductive vias interconnect the external pads with the internal components.
In packages of the Olenick et al design, the top surface of the substrate becomes very crowded. The semiconductor dice mounted thereon require surface area. In addition, the sealing cover and external pads use some of the surface. Surface wiring usually consumers additional space. All of the space consumed on the surface forces the package designer to enlarge the package and thereby decrease the package density. With an enlarged package comes the associated increased expense.
Alternatively, the package designer may increase the lead density at the surface by decreasing the space between the bond pads. However, there are practical limits to how closely the bond pads may be located. The closer the bond pad spacing the more difficult attachment operations between bond pads and the leadframe become, often also increasing the cost.
There are a variety of proposals for packages which overcome the basic surface area limitation of the package illustrated by Olenick et al. Typically these proposals suggest embedding the active components within a multilayer package. Exemplary is U.S. Pat. No. 4,727,410 by Higgins. Higgins discloses a multilayer multichip module that uses chip carriers. Each chip carrier may be equipped with both circuit lines and test vias. The chip carriers are three dimensional structures that, after assembly, are mounted to a cube. Each cube may carry four or more chip carriers.
The Higgins invention is deficient in that the disclosed chip carriers are not readily manufactured. Further, the final structure is complex and rework is a significant issue. The Higgins vias also extend to the surface, and, where formed to be accessible after package assembly, would necessarily be exposed. These exposed vias present a hazard due to the possibility of contact between the vias and neighboring components. Even in non-contact, if there is a conductive body mounted immediately adjacent these vias, the possibility exists for electromagnetic coupling therebetween. In practice, the Higgins package must be further encapsulated to isolate the circuitry from surroundings.
As is known, testing prior to final assembly does not identify all defects. The embedding of the semiconductor dice as Higgins does makes any rework required after final assembly difficult or impossible. Yields necessarily suffer and costs increase.
There still exists a need for test points external to the sealed package. External test points provide for adequate testing of the dice and circuitry. Rework is then done without destruction of the dice or package. This would most desirably be achieved using standard package designs and affordable, reliable production methods.